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authorMichel Dänzer <michel.daenzer@amd.com>2012-03-14 20:12:42 +0400
committerDave Airlie <airlied@redhat.com>2012-03-20 12:47:46 +0400
commit0349af70da5e590793986a0e03dbf2a435f75103 (patch)
treec4104646049fcf3862397cac1b51284bbd48e1b9 /drivers/gpu/drm/radeon/radeon_legacy_crtc.c
parentc4353016dac10133fa5d8535af83f0c4845a2915 (diff)
downloadlinux-0349af70da5e590793986a0e03dbf2a435f75103.tar.xz
drm/radeon: Restrict offset for legacy display engine.
The hardware only takes 27 bits for the offset, so larger offsets are truncated, and the display shows random bits other than the intended ones. Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_legacy_crtc.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_legacy_crtc.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
index 25a19c483075..210317c7045e 100644
--- a/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
+++ b/drivers/gpu/drm/radeon/radeon_legacy_crtc.c
@@ -419,7 +419,9 @@ int radeon_crtc_do_set_base(struct drm_crtc *crtc,
r = radeon_bo_reserve(rbo, false);
if (unlikely(r != 0))
return r;
- r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
+ /* Only 27 bit offset for legacy CRTC */
+ r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27,
+ &base);
if (unlikely(r != 0)) {
radeon_bo_unreserve(rbo);
return -EINVAL;