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author | Dave Airlie <airlied@redhat.com> | 2014-06-10 07:09:01 +0400 |
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committer | Dave Airlie <airlied@redhat.com> | 2014-06-10 07:09:01 +0400 |
commit | 5b9adbd30d32a6176f6cb102f6fe73426636ed7b (patch) | |
tree | d04c136dc7f08ca8af9364b090d55eaead22dbbb /drivers/gpu/drm/radeon/radeon_fence.c | |
parent | f95aeb17f57c4c98b7f33627e5f51353fd094a93 (diff) | |
parent | 685d54b330d0f15c4f6c7bdf51e009aab0d6a750 (diff) | |
download | linux-5b9adbd30d32a6176f6cb102f6fe73426636ed7b.tar.xz |
Merge branch 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux into drm-next
Some additional patches for radeon for 3.16 now that -fixes has been merged.
- Gart fix for all asics r6xx+
- Add some VM tuning parameters
- misc fixes
* 'drm-next-3.16' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: Move fb update from radeon_flip_work_func to radeon_crtc_page_flip
drm/radeon/dpm: powertune updates for SI
Revert "drm/radeon: use variable UVD clocks"
drm/radeon: add query for number of active CUs
drm/radeon: add debugfs file to trigger GPU reset
drm/radeon: make vm_block_size a module parameter
drm/radeon: make VM size a module parameter (v2)
drm/radeon: rename alt_domain to allowed_domains
drm/radeon: use the SDMA on for buffer moves on CIK again
drm/radeon: remove range check from *_gart_set_page
drm/radeon: stop poisoning the GART TLB
drm/radeon: hdmi deep color modes must obey clock limit of sink.
drm/edid: Store all supported hdmi deep color modes in drm_display_info
drm/radeon: add missing vce init case for hawaii
drm/radeon: use lower_32_bits where appropriate
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_fence.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_fence.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c index a77b1c13ea43..913787085dfa 100644 --- a/drivers/gpu/drm/radeon/radeon_fence.c +++ b/drivers/gpu/drm/radeon/radeon_fence.c @@ -819,15 +819,35 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data) return 0; } +/** + * radeon_debugfs_gpu_reset - manually trigger a gpu reset + * + * Manually trigger a gpu reset at the next fence wait. + */ +static int radeon_debugfs_gpu_reset(struct seq_file *m, void *data) +{ + struct drm_info_node *node = (struct drm_info_node *) m->private; + struct drm_device *dev = node->minor->dev; + struct radeon_device *rdev = dev->dev_private; + + down_read(&rdev->exclusive_lock); + seq_printf(m, "%d\n", rdev->needs_reset); + rdev->needs_reset = true; + up_read(&rdev->exclusive_lock); + + return 0; +} + static struct drm_info_list radeon_debugfs_fence_list[] = { {"radeon_fence_info", &radeon_debugfs_fence_info, 0, NULL}, + {"radeon_gpu_reset", &radeon_debugfs_gpu_reset, 0, NULL} }; #endif int radeon_debugfs_fence_init(struct radeon_device *rdev) { #if defined(CONFIG_DEBUG_FS) - return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 1); + return radeon_debugfs_add_files(rdev, radeon_debugfs_fence_list, 2); #else return 0; #endif |