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| author | Christian König <christian.koenig@amd.com> | 2014-04-23 22:46:06 +0400 |
|---|---|---|
| committer | Christian König <christian.koenig@amd.com> | 2014-05-01 14:27:42 +0400 |
| commit | f5d636d2a74b755879feec35e14a259de52ccc07 (patch) | |
| tree | 2521a37a27117a354e681d044cf357656144ac37 /drivers/gpu/drm/radeon/radeon_display.c | |
| parent | e45187620f9fc103edf68fa5ea78e73033e1668c (diff) | |
| download | linux-f5d636d2a74b755879feec35e14a259de52ccc07.tar.xz | |
drm/radeon: use pflip irq on R600+ v2
Testing the update pending bit directly after issuing an
update is nonsense cause depending on the pixel clock the
CRTC needs a bit of time to execute the flip even when we
are in the VBLANK period.
This is just a non invasive patch to solve the problem at
hand, a more complete and cleaner solution should follow
in the next merge window.
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564
v2: fix source IDs for CRTC2-6
Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_display.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_display.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c index 8d99d5ee8014..14bd701e316c 100644 --- a/drivers/gpu/drm/radeon/radeon_display.c +++ b/drivers/gpu/drm/radeon/radeon_display.c @@ -284,6 +284,10 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id) u32 update_pending; int vpos, hpos; + /* can happen during initialization */ + if (radeon_crtc == NULL) + return; + spin_lock_irqsave(&rdev->ddev->event_lock, flags); work = radeon_crtc->unpin_work; if (work == NULL || |