diff options
| author | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-06-18 02:55:13 +0300 |
|---|---|---|
| committer | Rafael J. Wysocki <rafael.j.wysocki@intel.com> | 2016-06-18 02:55:13 +0300 |
| commit | 9d066a252786e1a18484a6283f82614d42a9f4ac (patch) | |
| tree | 72188d2f86b3d0c4100257c8d5734f2c648a8bc7 /drivers/gpu/drm/radeon/radeon_asic.c | |
| parent | 79ee2e8f730411a30b271d5f9cdeae189fa66174 (diff) | |
| parent | b00345d1994d588fa2687e1238fcd542f0320cba (diff) | |
| download | linux-9d066a252786e1a18484a6283f82614d42a9f4ac.tar.xz | |
Merge branches 'pm-opp' and 'pm-cpufreq-fixes'
* pm-opp:
PM / OPP: Add 'UNKNOWN' status for shared_opp in struct opp_table
* pm-cpufreq-fixes:
cpufreq: intel_pstate: Adjust _PSS[0] freqeuency if needed
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 7d5a36dd5094..bc5121d1a7bc 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c @@ -2324,6 +2324,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->num_crtc = 2; rdev->has_uvd = false; + rdev->has_vce = false; switch (rdev->family) { case CHIP_R100: @@ -2454,6 +2455,7 @@ int radeon_asic_init(struct radeon_device *rdev) /* set num crtcs */ rdev->num_crtc = 4; rdev->has_uvd = true; + rdev->has_vce = true; rdev->cg_flags = RADEON_CG_SUPPORT_VCE_MGCG; break; @@ -2470,10 +2472,13 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->num_crtc = 2; else rdev->num_crtc = 6; - if (rdev->family == CHIP_HAINAN) + if (rdev->family == CHIP_HAINAN) { rdev->has_uvd = false; - else + rdev->has_vce = false; + } else { rdev->has_uvd = true; + rdev->has_vce = true; + } switch (rdev->family) { case CHIP_TAHITI: rdev->cg_flags = @@ -2578,6 +2583,7 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic = &ci_asic; rdev->num_crtc = 6; rdev->has_uvd = true; + rdev->has_vce = true; if (rdev->family == CHIP_BONAIRE) { rdev->cg_flags = RADEON_CG_SUPPORT_GFX_MGCG | @@ -2678,6 +2684,7 @@ int radeon_asic_init(struct radeon_device *rdev) RADEON_PG_SUPPORT_SAMU;*/ } rdev->has_uvd = true; + rdev->has_vce = true; break; default: /* FIXME: not supported yet */ @@ -2689,6 +2696,11 @@ int radeon_asic_init(struct radeon_device *rdev) rdev->asic->pm.set_memory_clock = NULL; } + if (!radeon_uvd) + rdev->has_uvd = false; + if (!radeon_vce) + rdev->has_vce = false; + return 0; } |