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authorAlex Deucher <alexander.deucher@amd.com>2012-02-24 02:53:49 +0400
committerDave Airlie <airlied@redhat.com>2012-02-29 14:15:25 +0400
commit9e6f3d02c4d28e68a73d100f7719440196f636de (patch)
tree0885c4be2b740cd2f19c9d100fbce6ed7e737b6e /drivers/gpu/drm/radeon/radeon_asic.c
parent798bcf7341cd434f89a4ddd6882ac043b1399825 (diff)
downloadlinux-9e6f3d02c4d28e68a73d100f7719440196f636de.tar.xz
drm/radeon/kms: reorganize surface callbacks
tidy up the radeon_asic struct. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König<christian.koenig@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c103
1 files changed, 68 insertions, 35 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 4eaa5f1209b2..0a59f4810187 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -168,8 +168,10 @@ static struct radeon_asic r100_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -240,8 +242,10 @@ static struct radeon_asic r200_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -312,8 +316,10 @@ static struct radeon_asic r300_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -384,8 +390,10 @@ static struct radeon_asic r300_asic_pcie = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -456,9 +464,10 @@ static struct radeon_asic r420_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
-
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -529,8 +538,10 @@ static struct radeon_asic rs400_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &r100_hpd_init,
.fini = &r100_hpd_fini,
@@ -601,8 +612,10 @@ static struct radeon_asic rs600_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &rs600_hpd_init,
.fini = &rs600_hpd_fini,
@@ -673,8 +686,10 @@ static struct radeon_asic rs690_asic = {
.copy = &r200_copy_dma,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &rs600_hpd_init,
.fini = &rs600_hpd_fini,
@@ -745,8 +760,10 @@ static struct radeon_asic rv515_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &rs600_hpd_init,
.fini = &rs600_hpd_fini,
@@ -817,8 +834,10 @@ static struct radeon_asic r520_asic = {
.copy = &r100_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r100_set_surface_reg,
- .clear_surface_reg = r100_clear_surface_reg,
+ .surface = {
+ .set_reg = r100_set_surface_reg,
+ .clear_reg = r100_clear_surface_reg,
+ },
.hpd = {
.init = &rs600_hpd_init,
.fini = &rs600_hpd_fini,
@@ -888,8 +907,10 @@ static struct radeon_asic r600_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &r600_hpd_init,
.fini = &r600_hpd_fini,
@@ -959,8 +980,10 @@ static struct radeon_asic rs780_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &r600_hpd_init,
.fini = &r600_hpd_fini,
@@ -1030,8 +1053,10 @@ static struct radeon_asic rv770_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &r600_hpd_init,
.fini = &r600_hpd_fini,
@@ -1101,8 +1126,10 @@ static struct radeon_asic evergreen_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini,
@@ -1172,8 +1199,10 @@ static struct radeon_asic sumo_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini,
@@ -1243,8 +1272,10 @@ static struct radeon_asic btc_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini,
@@ -1343,8 +1374,10 @@ static struct radeon_asic cayman_asic = {
.copy = &r600_copy_blit,
.copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
},
- .set_surface_reg = r600_set_surface_reg,
- .clear_surface_reg = r600_clear_surface_reg,
+ .surface = {
+ .set_reg = r600_set_surface_reg,
+ .clear_reg = r600_clear_surface_reg,
+ },
.hpd = {
.init = &evergreen_hpd_init,
.fini = &evergreen_hpd_fini,
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-30 14:52:12 +0300