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authorDave Airlie <airlied@redhat.com>2014-02-27 08:39:30 +0400
committerDave Airlie <airlied@redhat.com>2014-02-27 08:39:30 +0400
commit4d538b79197901fecc42e746d515d07fd1089b62 (patch)
tree0551acabf260fcd7c0189a4e06bb608e31d1206e /drivers/gpu/drm/radeon/r100.c
parentc48cdd23ea5006c377b670bc3056fa7b63f92574 (diff)
parent82dc62a31ce3ed7b4eeea9c65a3b69e81e2ea688 (diff)
downloadlinux-4d538b79197901fecc42e746d515d07fd1089b62.tar.xz
Merge branch 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux into drm-next
So this is the initial pull request for radeon drm-next 3.15. Highlights: - VCE bringup including DPM support - Few cleanups for the ring handling code * 'drm-next-3.15' of git://people.freedesktop.org/~deathsimple/linux: drm/radeon: cleanup false positive lockup handling drm/radeon: drop radeon_ring_force_activity drm/radeon: drop drivers copy of the rptr drm/radeon/cik: enable/disable vce cg when encoding v2 drm/radeon: add support for vce 2.0 clock gating drm/radeon/dpm: properly enable/disable vce when vce pg is enabled drm/radeon/dpm: enable dynamic vce state switching v2 drm/radeon: add vce dpm support for KV/KB drm/radeon: enable vce dpm on CI drm/radeon: add vce dpm support for CI drm/radeon: fill in set_vce_clocks for CIK asics drm/radeon/dpm: fetch vce states from the vbios drm/radeon/dpm: fill in some initial vce infrastructure drm/radeon/dpm: move platform caps fetching to a separate function drm/radeon: add callback for setting vce clocks drm/radeon: add VCE version parsing and checking drm/radeon: add VCE ring query drm/radeon: initial VCE support v4 drm/radeon: fix CP semaphores on CIK
Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index ef024ce3f7cc..1690a2dc0721 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1193,7 +1193,6 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
WREG32(RADEON_CP_RB_CNTL, tmp);
udelay(10);
- ring->rptr = RREG32(RADEON_CP_RB_RPTR);
/* Set cp mode to bus mastering & enable cp*/
WREG32(RADEON_CP_CSQ_MODE,
REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -2523,11 +2522,9 @@ bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
rbbm_status = RREG32(R_000E40_RBBM_STATUS);
if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
- radeon_ring_lockup_update(ring);
+ radeon_ring_lockup_update(rdev, ring);
return false;
}
- /* force CP activities */
- radeon_ring_force_activity(rdev, ring);
return radeon_ring_test_lockup(rdev, ring);
}