diff options
author | Dave Airlie <airlied@redhat.com> | 2013-07-09 04:49:39 +0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2013-07-09 04:49:39 +0400 |
commit | 774d8e34e46506222bb5e2888e3ef42b2775715f (patch) | |
tree | 22b62340c42a82262d91078b19a2f5f3bfd12099 /drivers/gpu/drm/radeon/ni_dpm.c | |
parent | fd0932d7f80146f115671a165461c6f877620abb (diff) | |
parent | f4dec31861e938267d41a962f145edc7d81c8e92 (diff) | |
download | linux-774d8e34e46506222bb5e2888e3ef42b2775715f.tar.xz |
Merge branch 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux into drm-next
A few more DPM fixes based on user testing.
* 'drm-next-3.11' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon/dpm: implement vblank_too_short callback for si
drm/radeon/dpm: implement vblank_too_short callback for cayman
drm/radeon/dpm: implement vblank_too_short callback for btc
drm/radeon/dpm: implement vblank_too_short callback for evergreen
drm/radeon/dpm: implement vblank_too_short callback for 7xx
drm/radeon/dpm: add checks against vblank time
drm/radeon/dpm: add helper to calculate vblank time
drm/radeon: remove stray line in old pm code
drm/radeon/dpm: fix display_gap programming on rv7xx
drm/radeon/dpm: implement force performance level for TN
drm/radeon/dpm: implement force performance level for ON/LN
drm/radeon/dpm: implement force performance level for SI
drm/radeon/dpm: implement force performance level for cayman
drm/radeon/dpm: implement force performance levels for 7xx/eg/btc
drm/radeon/dpm: add infrastructure to force performance levels
drm/radeon: fix surface setup on r1xx
drm/radeon: add support for 3d perf states on older asics
drm/radeon: set default clocks for SI when DPM is disabled
Diffstat (limited to 'drivers/gpu/drm/radeon/ni_dpm.c')
-rw-r--r-- | drivers/gpu/drm/radeon/ni_dpm.c | 54 |
1 files changed, 46 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c index a4cb99c2da85..559cf24d51af 100644 --- a/drivers/gpu/drm/radeon/ni_dpm.c +++ b/drivers/gpu/drm/radeon/ni_dpm.c @@ -765,6 +765,19 @@ static void ni_calculate_leakage_for_v_and_t(struct radeon_device *rdev, ni_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage); } +bool ni_dpm_vblank_too_short(struct radeon_device *rdev) +{ + struct rv7xx_power_info *pi = rv770_get_pi(rdev); + u32 vblank_time = r600_dpm_get_vblank_time(rdev); + u32 switch_limit = pi->mem_gddr5 ? 450 : 300; + + if (vblank_time < switch_limit) + return true; + else + return false; + +} + static void ni_apply_state_adjust_rules(struct radeon_device *rdev, struct radeon_ps *rps) { @@ -775,7 +788,8 @@ static void ni_apply_state_adjust_rules(struct radeon_device *rdev, u16 vddc, vddci; int i; - if (rdev->pm.dpm.new_active_crtc_count > 1) + if ((rdev->pm.dpm.new_active_crtc_count > 1) || + ni_dpm_vblank_too_short(rdev)) disable_mclk_switching = true; else disable_mclk_switching = false; @@ -1037,13 +1051,37 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd 0 : -EINVAL; } -static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *rdev) +int ni_dpm_force_performance_level(struct radeon_device *rdev, + enum radeon_dpm_forced_level level) { - if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) - return -EINVAL; + struct radeon_ps *rps = rdev->pm.dpm.current_ps; + struct ni_ps *ps = ni_get_ps(rps); + u32 levels; - return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ? - 0 : -EINVAL; + if (level == RADEON_DPM_FORCED_LEVEL_HIGH) { + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) + return -EINVAL; + + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK) + return -EINVAL; + } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) { + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) + return -EINVAL; + + levels = ps->performance_level_count - 1; + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK) + return -EINVAL; + } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) { + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK) + return -EINVAL; + + if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK) + return -EINVAL; + } + + rdev->pm.dpm.forced_level = level; + + return 0; } static void ni_stop_smc(struct radeon_device *rdev) @@ -3831,9 +3869,9 @@ int ni_dpm_set_power_state(struct radeon_device *rdev) return ret; } - ret = ni_unrestrict_performance_levels_after_switch(rdev); + ret = ni_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO); if (ret) { - DRM_ERROR("ni_unrestrict_performance_levels_after_switch failed\n"); + DRM_ERROR("ni_dpm_force_performance_level failed\n"); return ret; } |