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author | Alex Deucher <alexander.deucher@amd.com> | 2013-03-28 18:46:29 +0400 |
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committer | Alex Deucher <alexander.deucher@amd.com> | 2013-06-28 03:40:07 +0400 |
commit | 72dd2c54ee630701608c08fd85e0eaf75336e31c (patch) | |
tree | 4de60c6912f8a3db5b3df329c00d9415894d88c1 /drivers/gpu/drm/radeon/cypress_dpm.c | |
parent | 2c48febb47c60df91775366eb8c65556a1cdb3c8 (diff) | |
download | linux-72dd2c54ee630701608c08fd85e0eaf75336e31c.tar.xz |
drm/radeon/dpm: add dpm_set_power_state failure output (7xx-ni)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cypress_dpm.c')
-rw-r--r-- | drivers/gpu/drm/radeon/cypress_dpm.c | 26 |
1 files changed, 18 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/cypress_dpm.c b/drivers/gpu/drm/radeon/cypress_dpm.c index f90e5498785c..0097ff725e67 100644 --- a/drivers/gpu/drm/radeon/cypress_dpm.c +++ b/drivers/gpu/drm/radeon/cypress_dpm.c @@ -1971,34 +1971,44 @@ int cypress_dpm_set_power_state(struct radeon_device *rdev) int ret; ret = rv770_restrict_performance_levels_before_switch(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_restrict_performance_levels_before_switch failed\n"); return ret; - + } if (eg_pi->pcie_performance_request) cypress_notify_link_speed_change_before_state_change(rdev, new_ps, old_ps); rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps); ret = rv770_halt_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_halt_smc failed\n"); return ret; + } ret = cypress_upload_sw_state(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_sw_state failed\n"); return ret; - + } if (eg_pi->dynamic_ac_timing) { ret = cypress_upload_mc_reg_table(rdev, new_ps); - if (ret) + if (ret) { + DRM_ERROR("cypress_upload_mc_reg_table failed\n"); return ret; + } } cypress_program_memory_timing_parameters(rdev, new_ps); ret = rv770_resume_smc(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_resume_smc failed\n"); return ret; + } ret = rv770_set_sw_state(rdev); - if (ret) + if (ret) { + DRM_ERROR("rv770_set_sw_state failed\n"); return ret; + } rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps); if (eg_pi->pcie_performance_request) |