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| author | Alex Deucher <alexander.deucher@amd.com> | 2014-01-10 01:35:39 +0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2014-01-20 21:05:14 +0400 |
| commit | da9e07e6f53eaac4e838bc8c987d87c5769be724 (patch) | |
| tree | 22f5c16da6bad987a552564265f002cfbcc39d3c /drivers/gpu/drm/radeon/cik_sdma.c | |
| parent | ca113f6baeb314a66463c35565b4f7955c484000 (diff) | |
| download | linux-da9e07e6f53eaac4e838bc8c987d87c5769be724.tar.xz | |
drm/radeon/cik: use POLL_REG_MEM special op for sDMA HDP flush
This is the preferred flushing method on CIK.
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/cik_sdma.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index d7e51c06d597..9abea87a9213 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c @@ -168,13 +168,21 @@ static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev, int ridx) { struct radeon_ring *ring = &rdev->ring[ridx]; + u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) | + SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */ + u32 ref_and_mask; - /* We should be using the new POLL_REG_MEM special op packet here - * but it causes sDMA to hang sometimes - */ - radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); - radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2); - radeon_ring_write(ring, 0); + if (ridx == R600_RING_TYPE_DMA_INDEX) + ref_and_mask = SDMA0; + else + ref_and_mask = SDMA1; + + radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits)); + radeon_ring_write(ring, GPU_HDP_FLUSH_DONE); + radeon_ring_write(ring, GPU_HDP_FLUSH_REQ); + radeon_ring_write(ring, ref_and_mask); /* reference */ + radeon_ring_write(ring, ref_and_mask); /* mask */ + radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */ } /** |