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| author | Marek Vasut <marex@denx.de> | 2020-07-28 23:12:42 +0300 |
|---|---|---|
| committer | Sam Ravnborg <sam@ravnborg.org> | 2020-08-02 10:09:59 +0300 |
| commit | 07c913c4d7101fbef0bac738740aa2bba395d157 (patch) | |
| tree | dc8d2a0b4745655bcfac93f3435d14548debbf05 /drivers/gpu/drm/panel | |
| parent | 44de5cee20387b61477f44689f0f81f08aeddbe6 (diff) | |
| download | linux-07c913c4d7101fbef0bac738740aa2bba395d157.tar.xz | |
drm/panel: simple: Add Chefree CH101OLHLWH-002 panel
Add support for the Chefree CH101OLHLWH-002 10.1" (1280x800)
color TFT LCD panel, connected over LVDS.
Timings are taken from the datasheet version P0.5.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: dri-devel@lists.freedesktop.org
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Sam Ravnborg <sam@ravnborg.org>
Link: https://patchwork.freedesktop.org/patch/msgid/20200728201242.4336-3-marex@denx.de
Diffstat (limited to 'drivers/gpu/drm/panel')
| -rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 67ca543e74e8..3787748b5bd0 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1442,6 +1442,36 @@ static const struct panel_desc cdtech_s070wv95_ct16 = { }, }; +static const struct display_timing chefree_ch101olhlwh_002_timing = { + .pixelclock = { 68900000, 71100000, 73400000 }, + .hactive = { 1280, 1280, 1280 }, + .hfront_porch = { 65, 80, 95 }, + .hback_porch = { 64, 79, 94 }, + .hsync_len = { 1, 1, 1 }, + .vactive = { 800, 800, 800 }, + .vfront_porch = { 7, 11, 14 }, + .vback_porch = { 7, 11, 14 }, + .vsync_len = { 1, 1, 1 }, + .flags = DISPLAY_FLAGS_DE_HIGH, +}; + +static const struct panel_desc chefree_ch101olhlwh_002 = { + .timings = &chefree_ch101olhlwh_002_timing, + .num_timings = 1, + .bpc = 8, + .size = { + .width = 217, + .height = 135, + }, + .delay = { + .enable = 200, + .disable = 200, + }, + .bus_flags = DRM_BUS_FLAG_DE_HIGH, + .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, + .connector_type = DRM_MODE_CONNECTOR_LVDS, +}; + static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { .clock = 66770, .hdisplay = 800, @@ -3872,6 +3902,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "cdtech,s070wv95-ct16", .data = &cdtech_s070wv95_ct16, }, { + .compatible = "chefree,ch101olhlwh-002", + .data = &chefree_ch101olhlwh_002, + }, { .compatible = "chunghwa,claa070wp03xg", .data = &chunghwa_claa070wp03xg, }, { |