diff options
author | Caesar Wang <wxt@rock-chips.com> | 2016-12-14 06:19:56 +0300 |
---|---|---|
committer | Thierry Reding <treding@nvidia.com> | 2017-01-26 12:34:17 +0300 |
commit | cac1a41125e7a871c630fb6ca3c5a9337e60e65d (patch) | |
tree | 1261703aa69c5b3ce7a686331fa674dda92d0bb4 /drivers/gpu/drm/panel | |
parent | 095790b750686190410e83d1bb4bf496e99f56cf (diff) | |
download | linux-cac1a41125e7a871c630fb6ca3c5a9337e60e65d.tar.xz |
drm/panel: simple: Add support BOE NV101WXMN51
The BOE NV101WXMN51 is a 10.1" WXGA color active matrix TFT LCD module
using amorphous silicon TFT's as an active switching devices. It can be
supported by the simple-panel driver.
Read the panel default EDID information:
EDID MODE DETAILS
name = <NULL>
pixel_clock = 71900
lvds_dual_channel = 0
refresh = 0
ha = 1280
hbl = 160
hso = 48
hspw = 32
hborder = 0
va = 800
vbl = 32
vso = 3
vspw = 5
vborder = 0
phsync = +
pvsync = -
x_mm = 0
y_mm = 0
drm_display_mode
.hdisplay = 1280
.hsync_start = 1328
.hsync_end = 1360
.htotal = 1440
.vdisplay = 800
.vsync_start = 803
.vsync_end = 808
.vtotal = 832
There are two modes in the EDID:
Detailed mode1: Clock 71.900 MHz, 216 mm x 135 mm
1280 1328 1360 1440 hborder 0
800 803 808 832 vborder 0
+hsync -vsync
Detailed mode2: Clock 57.500 MHz, 216 mm x 135 mm
1280 1328 1360 1440 hborder 0
800 803 808 832 vborder 0
+hsync -vsync
Support both of these modes on the panel.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Stéphane Marchesin <marcheu@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/panel')
-rw-r--r-- | drivers/gpu/drm/panel/panel-simple.c | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 06aaf79de8c8..1ce25b569f00 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -668,6 +668,48 @@ static const struct panel_desc avic_tm070ddh03 = { }, }; +static const struct drm_display_mode boe_nv101wxmn51_modes[] = { + { + .clock = 71900, + .hdisplay = 1280, + .hsync_start = 1280 + 48, + .hsync_end = 1280 + 48 + 32, + .htotal = 1280 + 48 + 32 + 80, + .vdisplay = 800, + .vsync_start = 800 + 3, + .vsync_end = 800 + 3 + 5, + .vtotal = 800 + 3 + 5 + 24, + .vrefresh = 60, + }, + { + .clock = 57500, + .hdisplay = 1280, + .hsync_start = 1280 + 48, + .hsync_end = 1280 + 48 + 32, + .htotal = 1280 + 48 + 32 + 80, + .vdisplay = 800, + .vsync_start = 800 + 3, + .vsync_end = 800 + 3 + 5, + .vtotal = 800 + 3 + 5 + 24, + .vrefresh = 48, + }, +}; + +static const struct panel_desc boe_nv101wxmn51 = { + .modes = boe_nv101wxmn51_modes, + .num_modes = ARRAY_SIZE(boe_nv101wxmn51_modes), + .bpc = 8, + .size = { + .width = 217, + .height = 136, + }, + .delay = { + .prepare = 210, + .enable = 50, + .unprepare = 160, + }, +}; + static const struct drm_display_mode chunghwa_claa070wp03xg_mode = { .clock = 66770, .hdisplay = 800, @@ -1748,6 +1790,9 @@ static const struct of_device_id platform_of_match[] = { .compatible = "avic,tm070ddh03", .data = &avic_tm070ddh03, }, { + .compatible = "boe,nv101wxmn51", + .data = &boe_nv101wxmn51, + }, { .compatible = "chunghwa,claa070wp03xg", .data = &chunghwa_claa070wp03xg, }, { |