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authorBen Skeggs <bskeggs@redhat.com>2010-02-12 04:11:54 +0300
committerBen Skeggs <bskeggs@redhat.com>2010-02-25 08:08:33 +0300
commitd87897d4c853a5c136f60efa858d0d4cb3740f57 (patch)
treea783a205911c993d991776317472b219cea08915 /drivers/gpu/drm/nouveau/nouveau_dma.c
parent2ccb04ecc704618d9cd2e26aad067dbb2a057366 (diff)
downloadlinux-d87897d4c853a5c136f60efa858d0d4cb3740f57.tar.xz
drm/nv50: make pushbuf dma object cover entire vm
This allows us to submit push buffers from any memtype to the hardware. We'll need this ability for VRAM index buffers at some point. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/nouveau_dma.c')
-rw-r--r--drivers/gpu/drm/nouveau/nouveau_dma.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index b9c80bb17250..679b03c28df1 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -182,12 +182,12 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
int delta, int dwords)
{
struct nouveau_bo *pb = chan->pushbuf_bo;
- uint64_t offset = (bo->bo.mem.mm_node->start << PAGE_SHIFT) + delta;
+ uint64_t offset = bo->bo.offset + delta;
int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
BUG_ON(chan->dma.ib_free < 1);
- nouveau_bo_wr32(pb, ip++, offset);
- nouveau_bo_wr32(pb, ip++, dwords << 10);
+ nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
+ nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | dwords << 10);
chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
nvchan_wr32(chan, 0x8c, chan->dma.ib_put);