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authorAlexandre Courbot <acourbot@nvidia.com>2016-04-01 05:37:44 +0300
committerBen Skeggs <bskeggs@redhat.com>2016-04-06 09:06:51 +0300
commit34440ed697aed2588d3e99bbdc75700a967bd1bd (patch)
tree035dc71ef053b46ba0231a902a14890d6ca4931c /drivers/gpu/drm/nouveau/include
parent52829d4fabaf71748f16126d421dbefbfcf1319a (diff)
downloadlinux-34440ed697aed2588d3e99bbdc75700a967bd1bd.tar.xz
drm/nouveau/tegra: acquire and enable reference clock if needed
GM20B requires an extra clock compared to GK20A. Add that information into the platform data and acquire and enable this clock if necessary. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/nouveau/include')
-rw-r--r--drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
index 16641cec18a2..b5370cb56e3c 100644
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/tegra.h
@@ -11,6 +11,7 @@ struct nvkm_device_tegra {
struct reset_control *rst;
struct clk *clk;
+ struct clk *clk_ref;
struct clk *clk_pwr;
struct regulator *vdd;
@@ -36,6 +37,10 @@ struct nvkm_device_tegra_func {
* bypassed). A value of 0 means an IOMMU is never used.
*/
u8 iommu_bit;
+ /*
+ * Whether the chip requires a reference clock
+ */
+ bool require_ref_clk;
};
int nvkm_device_tegra_new(const struct nvkm_device_tegra_func *,