diff options
| author | Jordan Crouse <jcrouse@codeaurora.org> | 2018-02-01 22:15:16 +0300 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2018-02-20 18:41:22 +0300 |
| commit | c5e3548c295ace44c2ec8c3af1c10e82bc47f9b3 (patch) | |
| tree | 8b237973ae71b2aafa1e8e8569fa057595317e8a /drivers/gpu/drm/msm/adreno/a3xx_gpu.c | |
| parent | f306953fdb1145020dd2a838698792d686feb2e3 (diff) | |
| download | linux-c5e3548c295ace44c2ec8c3af1c10e82bc47f9b3.tar.xz | |
drm/msm/adreno: Define a list of firmware files to load per target
The number and type of firmware files required differs for each
target. Instead of using a fixed struct member for each possible
firmware file use a generic list of files that should be loaded
on boot. Use some semi-target specific enums to help each target
find the appropriate firmware(s) that it needs to load.
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/adreno/a3xx_gpu.c')
| -rw-r--r-- | drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 4baef2738178..1dd84d3489ae 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -256,8 +256,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu) */ /* Load PM4: */ - ptr = (uint32_t *)(adreno_gpu->pm4->data); - len = adreno_gpu->pm4->size / 4; + ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PM4]->data); + len = adreno_gpu->fw[ADRENO_FW_PM4]->size / 4; DBG("loading PM4 ucode version: %x", ptr[1]); gpu_write(gpu, REG_AXXX_CP_DEBUG, @@ -268,8 +268,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_AXXX_CP_ME_RAM_DATA, ptr[i]); /* Load PFP: */ - ptr = (uint32_t *)(adreno_gpu->pfp->data); - len = adreno_gpu->pfp->size / 4; + ptr = (uint32_t *)(adreno_gpu->fw[ADRENO_FW_PFP]->data); + len = adreno_gpu->fw[ADRENO_FW_PFP]->size / 4; DBG("loading PFP ucode version: %x", ptr[5]); gpu_write(gpu, REG_A3XX_CP_PFP_UCODE_ADDR, 0); |