diff options
| author | Rob Clark <robdclark@gmail.com> | 2013-12-01 02:51:47 +0400 |
|---|---|---|
| committer | Rob Clark <robdclark@gmail.com> | 2014-01-09 23:44:06 +0400 |
| commit | 06c0dd96bfbba8a9368ffd7c4b12d3bfed37001d (patch) | |
| tree | 806d07197b4fd3ab0d73885329f7de1d890f22d6 /drivers/gpu/drm/msm/NOTES | |
| parent | dada25bd22a52a4351357209a8c227070cfd406d (diff) | |
| download | linux-06c0dd96bfbba8a9368ffd7c4b12d3bfed37001d.tar.xz | |
drm/msm: add mdp5/apq8x74
Add support for the new MDP5 display controller block. The mapping
between parts of the display controller and KMS is:
plane -> PIPE{RGBn,VIGn} \
crtc -> LM (layer mixer) |-> MDP "device"
encoder -> INTF /
connector -> HDMI/DSI/eDP/etc --> other device(s)
Unlike MDP4, it appears we can get by with a single encoder, rather
than needing a different implementation for DTV, DSI, etc. (Ie. the
register interface is same, just different bases.)
Also unlike MDP4, all the IRQs for other blocks (HDMI, DSI, etc) are
routed through MDP.
And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from
which blocks need to be allocated to the active pipes based on fetch
stride.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat (limited to 'drivers/gpu/drm/msm/NOTES')
| -rw-r--r-- | drivers/gpu/drm/msm/NOTES | 20 |
1 files changed, 19 insertions, 1 deletions
diff --git a/drivers/gpu/drm/msm/NOTES b/drivers/gpu/drm/msm/NOTES index e036f6c1db94..9c4255b98021 100644 --- a/drivers/gpu/drm/msm/NOTES +++ b/drivers/gpu/drm/msm/NOTES @@ -4,7 +4,7 @@ In the current snapdragon SoC's, we have (at least) 3 different display controller blocks at play: + MDP3 - ?? seems to be what is on geeksphone peak device + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410) - + MDSS - snapdragon 800 + + MDP5 - snapdragon 800 (I don't have a completely clear picture on which display controller maps to which part #) @@ -46,6 +46,24 @@ and treat the MDP4 block's irq as "the" irq. Even though the connectors may have their own irqs which they install themselves. For this reason the display controller is the "master" device. +For MDP5, the mapping is: + + plane -> PIPE{RGBn,VIGn} \ + crtc -> LM (layer mixer) |-> MDP "device" + encoder -> INTF / + connector -> HDMI/DSI/eDP/etc --> other device(s) + +Unlike MDP4, it appears we can get by with a single encoder, rather +than needing a different implementation for DTV, DSI, etc. (Ie. the +register interface is same, just different bases.) + +Also unlike MDP4, with MDP5 all the IRQs for other blocks (HDMI, DSI, +etc) are routed through MDP. + +And finally, MDP5 has this "Shared Memory Pool" (called "SMP"), from +which blocks need to be allocated to the active pipes based on fetch +stride. + Each connector probably ends up being a separate device, just for the logistics of finding/mapping io region, irq, etc. Idealy we would have a better way than just stashing the platform device in a global |