diff options
| author | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-05-20 14:04:42 +0300 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2019-05-22 12:11:10 +0300 |
| commit | cbe3e1d103793705204b29c6952faed537c41fe1 (patch) | |
| tree | afdf0fe110e55108d4e11c2b0262c8d3e4924d48 /drivers/gpu/drm/i915 | |
| parent | fde938867b92607d1108fa42cf7fbfcbab8457c8 (diff) | |
| download | linux-cbe3e1d103793705204b29c6952faed537c41fe1.tar.xz | |
drm/i915/icl: Add WaDisableBankHangMode
Disable GPU hang by default on unrecoverable ECC cache errors.
v2:
* Rebase.
v3:
* Use intel_uncore_read. (Chris)
Fixes: cc38cae7c4e9 ("drm/i915/icl: Introduce initial Icelake Workarounds")
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190520110442.403-2-tvrtko.ursulin@linux.intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 3 |
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index d692b83583fa..990b278a36d1 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -529,6 +529,12 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine, { struct drm_i915_private *i915 = engine->i915; + /* WaDisableBankHangMode:icl */ + wa_write(wal, + GEN8_L3CNTLREG, + intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) | + GEN8_ERRDETBCTRL); + /* Wa_1604370585:icl (pre-prod) * Formerly known as WaPushConstantDereferenceHoldDisable */ diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e97c47fca645..87e8780711d7 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7621,6 +7621,9 @@ enum { #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) +#define GEN8_L3CNTLREG _MMIO(0x7034) + #define GEN8_ERRDETBCTRL (1 << 9) + #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC (1 << 11) |