diff options
| author | Chris Wilson <chris@chris-wilson.co.uk> | 2020-03-11 13:36:40 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2020-03-20 17:04:38 +0300 |
| commit | e50c951ea6ff17e7b1f2a5c118506b58b474ded3 (patch) | |
| tree | e6f0d6bcbeb514d2bd4df6c05c96422620364d8e /drivers/gpu/drm/i915 | |
| parent | cb7adfd6ad12a11902ebe374bec7fd4efa2cec1c (diff) | |
| download | linux-e50c951ea6ff17e7b1f2a5c118506b58b474ded3.tar.xz | |
drm/i915/gt: Restrict gen7 w/a batch to Haswell
The residual w/a batch is causing system instablity on Ivybridge and
Baytrail under some workloads, so disable until resolved.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1405
Fixes: 47f8253d2b89 ("drm/i915/gen7: Clear all EU/L3 residual contexts")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
Cc: Akeem G Abodunrin <akeem.g.abodunrin@intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200311103640.26572-1-chris@chris-wilson.co.uk
(cherry picked from commit a62774782b994026ac3198bf115717d55d536166)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_ring_submission.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c index 1424582e4a9b..fdc3f10e12aa 100644 --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c @@ -2088,7 +2088,7 @@ int intel_ring_submission_setup(struct intel_engine_cs *engine) GEM_BUG_ON(timeline->hwsp_ggtt != engine->status_page.vma); - if (IS_GEN(engine->i915, 7) && engine->class == RENDER_CLASS) { + if (IS_HASWELL(engine->i915) && engine->class == RENDER_CLASS) { err = gen7_ctx_switch_bb_init(engine); if (err) goto err_ring_unpin; |