diff options
| author | Imre Deak <imre.deak@intel.com> | 2015-05-19 17:05:41 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-05-21 15:02:06 +0300 |
| commit | 2a0ee94fef9aa87f23070693764175982700f0f5 (patch) | |
| tree | 9eaeb0db900d6c06ff934f0329c5037b370ea0d9 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 118182e9d7d5afa0c7c10f568afb46ab78b462e9 (diff) | |
| download | linux-2a0ee94fef9aa87f23070693764175982700f0f5.tar.xz | |
drm/i915/bxt: fix WaForceContextSaveRestoreNonCoherent on steppings B0+
On B0 and C0 steppings the workaround enable bit would be overriden by
default, so the overriding must be disabled.
The WA was added in
commit 83a24979c40ebbf0fa0cd14df16f74142f373cd3
Author: Nick Hoath <nicholas.hoath@intel.com>
Date: Fri Apr 10 13:12:26 2015 +0100
drm/i915/bxt: Add WaForceContextSaveRestoreNonCoherent
Spotted-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_ringbuffer.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 461b9befa776..a071b1062e30 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -1043,6 +1043,7 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint32_t tmp; gen9_init_workarounds(ring); @@ -1058,8 +1059,10 @@ static int bxt_init_workarounds(struct intel_engine_cs *ring) } /* WaForceContextSaveRestoreNonCoherent:bxt */ - WA_SET_BIT_MASKED(HDC_CHICKEN0, - HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT); + tmp = HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT; + if (INTEL_REVID(dev) >= BXT_REVID_B0) + tmp |= HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE; + WA_SET_BIT_MASKED(HDC_CHICKEN0, tmp); return 0; } |