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| author | José Roberto de Souza <jose.souza@intel.com> | 2018-03-29 01:30:43 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2018-03-30 20:18:07 +0300 |
| commit | fe36181be371f3d98441cc23ccbfa89783fa55b1 (patch) | |
| tree | d80d9ce16506775d98860b7016efb40a7dadfe9a /drivers/gpu/drm/i915/intel_psr.c | |
| parent | 95f28d2ec75ac388a8cc988e2e5496ce4adef4e4 (diff) | |
| download | linux-fe36181be371f3d98441cc23ccbfa89783fa55b1.tar.xz | |
drm/i915/psr: Use PSR2 macro for PSR2
Cosmetic change.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-7-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_psr.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_psr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 5efddd920681..bec455e28943 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -382,7 +382,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) uint32_t val; uint8_t sink_latency; - val = idle_frames << EDP_PSR_IDLE_FRAME_SHIFT; + val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT; /* FIXME: selective update is probably totally broken because it doesn't * mesh at all with our frontbuffer tracking. And the hw alone isn't |