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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-05-21 19:01:50 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-06-05 12:00:37 +0400 |
| commit | d7fe0cc0f2e0b302b247caa4306915a06218e0be (patch) | |
| tree | 0a9ea5c2dd3fa52f149dff054cb95a45fbcbaf80 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 4548feb1fe1f17c0d7ad7acdd267a875b22e6910 (diff) | |
| download | linux-d7fe0cc0f2e0b302b247caa4306915a06218e0be.tar.xz | |
drm/i915: Fix DSPCLK_GATE_D for VLV
Fix the DSPCLK_GATE_D access for VLV. The code incorrectly tried to
poke at the ILK+ version of the register which is at the wrong offset.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index b970267bb5d4..50fe3d7303cb 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -4797,7 +4797,7 @@ static void valleyview_init_clock_gating(struct drm_device *dev) struct drm_i915_private *dev_priv = dev->dev_private; int pipe; - I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); + I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); /* WaDisableEarlyCull:vlv */ I915_WRITE(_3D_CHICKEN3, |