diff options
| author | Zhenyu Wang <zhenyuw@linux.intel.com> | 2012-10-30 15:16:34 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-12 02:51:04 +0400 |
| commit | 263b30d4b1a52432075069070328cfa641179f92 (patch) | |
| tree | 4c3b4fa521724050ef9f203b720ab67b4d3c4818 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | 14f86147a90cb47db7ccfd90bf14f830fb34fba9 (diff) | |
| download | linux-263b30d4b1a52432075069070328cfa641179f92.tar.xz | |
drm/i915: Fix HSW power well control state read
Fix power well control state by reading real register offset.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index f85043ca41b5..59c31f6238c1 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev) if ((well & HSW_PWR_WELL_STATE) == 0) { I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE); - if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20)) + if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20)) DRM_ERROR("Error enabling power well %lx\n", power_wells[i]); } } |