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| author | Mahesh Kumar <mahesh1.kumar@intel.com> | 2016-12-01 18:49:35 +0300 |
|---|---|---|
| committer | Paulo Zanoni <paulo.r.zanoni@intel.com> | 2016-12-07 21:30:34 +0300 |
| commit | 4b7b2331885a1ab348178f3faf9dc6a4dccae01a (patch) | |
| tree | 38e704926acb34986900abf9f581f0c8ef89856a /drivers/gpu/drm/i915/intel_pm.c | |
| parent | a3a8986cb22aafd83681b7e783ca6d4963712989 (diff) | |
| download | linux-4b7b2331885a1ab348178f3faf9dc6a4dccae01a.tar.xz | |
drm/i915/kbl: IPC workaround for kabylake
Display Workarounds #1141
IPC (Isoch Priority Control) may cause underflows.
KBL WA: When IPC is enabled, watermark latency values must be increased
by 4us across all levels. This brings level 0 up to 6us.
Changes since V1:
- Add Workaround number in commit & code
Changes since V2 (from Paulo):
- Bikeshed the WA tag so it looks like the others
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20161201154940.24446-4-mahesh1.kumar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 9ea3eeed3385..315a1b339257 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3596,6 +3596,10 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, fb->modifier == I915_FORMAT_MOD_Yf_TILED; x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; + /* Display WA #1141: kbl. */ + if (IS_KABYLAKE(dev_priv) && dev_priv->ipc_enabled) + latency += 4; + if (apply_memory_bw_wa && x_tiled) latency += 15; |