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authorGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-23 15:29:43 +0300
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2017-10-23 15:29:43 +0300
commit7706abf5a0eb4c082897fd2a17a0ac0898e39666 (patch)
tree982d22365f1aeedc43a796ef816cf1b1fa8480a7 /drivers/gpu/drm/i915/intel_pm.c
parentca3c5858834f75543a4e2e115b1578c01558b2ce (diff)
parentbb176f67090ca54869fc1262c913aa69d2ede070 (diff)
downloadlinux-7706abf5a0eb4c082897fd2a17a0ac0898e39666.tar.xz
Merge 4.14-rc6 into staging-next
We want the IIO and staging driver fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ed662937ec3c..0a09f8ff6aff 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -8245,14 +8245,17 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
int high_prio_credits)
{
u32 misccpctl;
+ u32 val;
/* WaTempDisableDOPClkGating:bdw */
misccpctl = I915_READ(GEN7_MISCCPCTL);
I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- I915_WRITE(GEN8_L3SQCREG1,
- L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
- L3_HIGH_PRIO_CREDITS(high_prio_credits));
+ val = I915_READ(GEN8_L3SQCREG1);
+ val &= ~L3_PRIO_CREDITS_MASK;
+ val |= L3_GENERAL_PRIO_CREDITS(general_prio_credits);
+ val |= L3_HIGH_PRIO_CREDITS(high_prio_credits);
+ I915_WRITE(GEN8_L3SQCREG1, val);
/*
* Wait at least 100 clocks before re-enabling clock gating.