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author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-07-05 12:57:19 +0400 |
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committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-08-05 21:03:58 +0400 |
commit | 1fda9882ca0ba134134c5bf04b8d4f4f06b52649 (patch) | |
tree | efc825d9ed0b86cab8f23e1050eb236b86c11aaf /drivers/gpu/drm/i915/intel_pm.c | |
parent | 23297044ac70da5c87b1c1ef7d5cf32c84b2fd00 (diff) | |
download | linux-1fda9882ca0ba134134c5bf04b8d4f4f06b52649.tar.xz |
drm/i915: Don't pass "mem_value" to ilk_compute_fbc_wm
The FBC watermark doesn't depend on the latency value, so no point in
passing it in.
Note: It actually depends upon the latency, but only through priv_val
...
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[danvet: Add review comment from Paulo to the commit message.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
-rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6259072a288c..1a80787f4258 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -2260,8 +2260,7 @@ static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params, /* Only for WM_LP. */ static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params, - uint32_t pri_val, - uint32_t mem_value) + uint32_t pri_val) { if (!params->active) return 0; @@ -2284,7 +2283,7 @@ static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max, pri_val[pipe] = ilk_compute_pri_wm(p, mem_value, true); spr_val[pipe] = ilk_compute_spr_wm(p, mem_value); cur_val[pipe] = ilk_compute_cur_wm(p, mem_value); - fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe], mem_value); + fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]); } result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]); |