Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm

Pull drm updates from Dave Airlie:
 "This starts to support NVIDIA volta hardware with nouveau, and adds
  amdgpu support for the GPU in the Kabylake-G (the intel + radeon
  single package chip), along with some initial Intel icelake enabling.

  Summary:

  New Drivers:
   - v3d - driver for broadcom V3D V3.x+ hardware
   - xen-front - XEN PV display frontend

  core:
   - handle zpos normalization in the core
   - stop looking at legacy pointers in atomic paths
   - improved scheduler documentation
   - improved aspect ratio validation
   - aspect ratio support for 64:27 and 256:135
   - drop unused control node code.

  i915:
   - Icelake (ICL) enabling
   - GuC/HuC refactoring
   - PSR/PSR2 enabling and fixes
   - DPLL management refactoring
   - DP MST fixes
   - NV12 enabling
   - HDCP improvements
   - GEM/Execlist/reset improvements
   - GVT improvements
   - stolen memory first 4k fix

  amdgpu:
   - Vega 20 support
   - VEGAM support (Kabylake-G)
   - preOS scanout buffer reservation
   - power management gfxoff support for raven
   - SR-IOV fixes
   - Vega10 power profiles and clock voltage control
   - scatter/gather display support on CZ/ST

  amdkfd:
   - GFX9 dGPU support
   - userptr memory mapping

  nouveau:
   - major refactoring for Volta GV100 support

  tda998x:
   - HDMI i2c CEC support

  etnaviv:
   - removed unused logging code
   - license text cleanups
   - MMU handling improvements
   - timeout fence fix for 50 days uptime

  tegra:
   - IOMMU support in gr2d/gr3d drivers
   - zpos support

  vc4:
   - syncobj support
   - CTM, plane alpha and async cursor support

  analogix_dp:
   - HPD and aux chan fixes

  sun4i:
   - MIPI DSI support

  tilcdc:
   - clock divider fixes for OMAP-l138 LCDK board

  rcar-du:
   - R8A77965 support
   - dma-buf fences fixes
   - hardware indexed crtc/du group handling
   - generic zplane property support

  atmel-hclcdc:
   - generic zplane property support

  mediatek:
   - use generic video mode function

  exynos:
   - S5PV210 FIMD variant support
   - IPP v2 framework
   - more HW overlays support"

* tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits)
  drm/amdgpu: fix 32-bit build warning
  drm/exynos: fimc: signedness bug in fimc_setup_clocks()
  drm/exynos: scaler: fix static checker warning
  drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC
  drm/amd/display: Remove use of division operator for long longs
  drm/amdgpu: Update GFX info structure to match what vega20 used
  drm/amdgpu/pp: remove duplicate assignment
  drm/sched: add rcu_barrier after entity fini
  drm/amdgpu: move VM BOs on LRU again
  drm/amdgpu: consistenly use VM moved flag
  drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories
  drm/amdgpu: further optimize amdgpu_vm_handle_moved
  drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2
  drm/amdgpu: rework VM state machine lock handling v2
  drm/amdgpu: Add runtime VCN PG support
  drm/amdgpu: Enable VCN static PG by default on RV
  drm/amdgpu: Add VCN static PG support on RV
  drm/amdgpu: Enable VCN CG by default on RV
  drm/amdgpu: Add static CG control for VCN on RV
  drm/exynos: Fix default value for zpos plane property
  ...

1 files changed, 56 insertions, 19 deletions

diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 1f5cd572a7ff..39a4e4edda07 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -569,7 +569,8 @@ unlock:
 static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 				enum pipe pipe,
 				enum intel_pipe_crc_source *source,
-				uint32_t *val)
+				uint32_t *val,
+				bool set_wa)
 {
 	if (*source == INTEL_PIPE_CRC_SOURCE_AUTO)
 		*source = INTEL_PIPE_CRC_SOURCE_PF;
@@ -582,7 +583,7 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 		*val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB;
 		break;
 	case INTEL_PIPE_CRC_SOURCE_PF:
-		if ((IS_HASWELL(dev_priv) ||
+		if (set_wa && (IS_HASWELL(dev_priv) ||
 		     IS_BROADWELL(dev_priv)) && pipe == PIPE_A)
 			hsw_pipe_A_crc_wa(dev_priv, true);
 
@@ -600,7 +601,8 @@ static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv,
 
 static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 			       enum pipe pipe,
-			       enum intel_pipe_crc_source *source, u32 *val)
+			       enum intel_pipe_crc_source *source, u32 *val,
+			       bool set_wa)
 {
 	if (IS_GEN2(dev_priv))
 		return i8xx_pipe_crc_ctl_reg(source, val);
@@ -611,7 +613,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
 	else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv))
 		return ilk_pipe_crc_ctl_reg(source, val);
 	else
-		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
+		return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
 }
 
 static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
@@ -636,7 +638,7 @@ static int pipe_crc_set_source(struct drm_i915_private *dev_priv,
 		return -EIO;
 	}
 
-	ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val);
+	ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val, true);
 	if (ret != 0)
 		goto out;
 
@@ -764,13 +766,12 @@ display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o)
 {
 	int i;
 
-	for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++)
-		if (!strcmp(buf, pipe_crc_objects[i])) {
-			*o = i;
-			return 0;
-		}
+	i = match_string(pipe_crc_objects, ARRAY_SIZE(pipe_crc_objects), buf);
+	if (i < 0)
+		return i;
 
-	return -EINVAL;
+	*o = i;
+	return 0;
 }
 
 static int display_crc_ctl_parse_pipe(struct drm_i915_private *dev_priv,
@@ -796,13 +797,12 @@ display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s)
 		return 0;
 	}
 
-	for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++)
-		if (!strcmp(buf, pipe_crc_sources[i])) {
-			*s = i;
-			return 0;
-		}
+	i = match_string(pipe_crc_sources, ARRAY_SIZE(pipe_crc_sources), buf);
+	if (i < 0)
+		return i;
 
-	return -EINVAL;
+	*s = i;
+	return 0;
 }
 
 static int display_crc_ctl_parse(struct drm_i915_private *dev_priv,
@@ -916,7 +916,7 @@ int intel_pipe_crc_create(struct drm_minor *minor)
 int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
 			      size_t *values_cnt)
 {
-	struct drm_i915_private *dev_priv = crtc->dev->dev_private;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
 	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
 	enum intel_display_power_domain power_domain;
 	enum intel_pipe_crc_source source;
@@ -934,10 +934,11 @@ int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name,
 		return -EIO;
 	}
 
-	ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val);
+	ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val, true);
 	if (ret != 0)
 		goto out;
 
+	pipe_crc->source = source;
 	I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
 	POSTING_READ(PIPE_CRC_CTL(crtc->index));
 
@@ -959,3 +960,39 @@ out:
 
 	return ret;
 }
+
+void intel_crtc_enable_pipe_crc(struct intel_crtc *intel_crtc)
+{
+	struct drm_crtc *crtc = &intel_crtc->base;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
+	u32 val = 0;
+
+	if (!crtc->crc.opened)
+		return;
+
+	if (get_new_crc_ctl_reg(dev_priv, crtc->index, &pipe_crc->source, &val, false) < 0)
+		return;
+
+	/* Don't need pipe_crc->lock here, IRQs are not generated. */
+	pipe_crc->skipped = 0;
+
+	I915_WRITE(PIPE_CRC_CTL(crtc->index), val);
+	POSTING_READ(PIPE_CRC_CTL(crtc->index));
+}
+
+void intel_crtc_disable_pipe_crc(struct intel_crtc *intel_crtc)
+{
+	struct drm_crtc *crtc = &intel_crtc->base;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index];
+
+	/* Swallow crc's until we stop generating them. */
+	spin_lock_irq(&pipe_crc->lock);
+	pipe_crc->skipped = INT_MIN;
+	spin_unlock_irq(&pipe_crc->lock);
+
+	I915_WRITE(PIPE_CRC_CTL(crtc->index), 0);
+	POSTING_READ(PIPE_CRC_CTL(crtc->index));
+	synchronize_irq(dev_priv->drm.irq);
+}