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| author | Christian König <christian.koenig@amd.com> | 2022-10-07 11:59:58 +0300 |
|---|---|---|
| committer | Christian König <christian.koenig@amd.com> | 2022-10-19 13:45:00 +0300 |
| commit | 01f2cf53844b01e691516b465df1b6ab01b03230 (patch) | |
| tree | 61880f8c6964143b2a54749808fa68734243c771 /drivers/gpu/drm/i915/intel_mchbar_regs.h | |
| parent | 7b476affcccfc7e644541a0a719f53fc7bd34c53 (diff) | |
| download | linux-01f2cf53844b01e691516b465df1b6ab01b03230.tar.xz | |
drm/amdgpu: use DRM_SCHED_FENCE_DONT_PIPELINE for VM updates
Make sure that we always have a CPU round trip to let the submission
code correctly decide if a TLB flush is necessary or not.
Signed-off-by: Christian König <christian.koenig@amd.com>
Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2113#note_1579296
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Luben Tuikov <luben.tuikov@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221014081553.114899-2-christian.koenig@amd.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_mchbar_regs.h')
0 files changed, 0 insertions, 0 deletions