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| author | Mika Kuoppala <mika.kuoppala@linux.intel.com> | 2015-08-06 17:00:59 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-08-14 18:50:38 +0300 |
| commit | cc53699b25b59eb1020af8064f99edd0014b7071 (patch) | |
| tree | d765423d428f05c019b467af8c9e55c8a9109a19 /drivers/gpu/drm/i915/intel_lrc.c | |
| parent | 9bd9dfb4f9a1edcbb561a80d00c234fbe11dc1a6 (diff) | |
| download | linux-cc53699b25b59eb1020af8064f99edd0014b7071.tar.xz | |
drm/i915: Use masked write for Context Status Buffer Pointer
This register needs to be updated with masked writes.
This was found by code inspection and comparison with Bspec and
doesn't seem to fix any known issue.
Signed-off-by: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Michel Thierry <michel.thierry@intel.com>
[danvet: Add note about impact.]
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_lrc.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_lrc.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 99bba8ece464..29347e7a9565 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -521,7 +521,7 @@ void intel_lrc_irq_handler(struct intel_engine_cs *ring) ring->next_context_status_buffer = write_pointer % 6; I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), - ((u32)ring->next_context_status_buffer & 0x07) << 8); + _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); } static int execlists_context_queue(struct drm_i915_gem_request *request) |