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| author | Damien Lespiau <damien.lespiau@intel.com> | 2015-03-06 21:50:48 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-18 00:30:06 +0300 |
| commit | 4c6c03be125e9d8477c2d8ef3c3280270956b1fe (patch) | |
| tree | 3880d0ccd3efafcc7b64e5be9760dc022675bdd1 /drivers/gpu/drm/i915/intel_drv.h | |
| parent | 5575f03a603d267e84ab3727f7241b8be5f7d8ee (diff) | |
| download | linux-4c6c03be125e9d8477c2d8ef3c3280270956b1fe.tar.xz | |
drm/i915/skl: Make gen8_irq_power_well_post_enable() take a pipe mask
While we only need to restore pipe B/C interrupt registers on BDW when
enabling the power well, skylake a bit more flexible and we'll also need
to restore the pipe A registers as it has its own power well that can be
toggled.
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_drv.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_drv.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index ff79dca2ff8e..c77128c67cf8 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -840,7 +840,8 @@ static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) } int intel_get_crtc_scanline(struct intel_crtc *crtc); -void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv); +void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, + unsigned int pipe_mask); /* intel_crt.c */ void intel_crt_init(struct drm_device *dev); |