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| author | Manasi Navare <manasi.d.navare@intel.com> | 2016-09-02 01:08:11 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2016-09-07 23:55:33 +0300 |
| commit | 81b9fd8fc68e9e0999efc604c4e5477b8d1982aa (patch) | |
| tree | cfd68e638787b33638d718a3244837acdbafe0ca /drivers/gpu/drm/i915/intel_dpll_mgr.h | |
| parent | 9a4edadaccea5ba9b73abaff8121e68dd0ff70bc (diff) | |
| download | linux-81b9fd8fc68e9e0999efc604c4e5477b8d1982aa.tar.xz | |
drm/i915: Split hsw_get_dpll()
Split out the DisplayPort and HDMI pll setup code into separate
functions and refactor the DP code that calculates the pll
so that it doesn't depend on crtc state.
This will be used for acquiring port pll when doing
upfront link training.
Reviewed-by: Durgadoss R <durgadoss.r@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.h')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dpll_mgr.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h index cb28f8df8701..aed74084f759 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h @@ -164,8 +164,14 @@ void intel_shared_dpll_init(struct drm_device *dev); bool bxt_ddi_dp_set_dpll_hw_state(int clock, struct intel_dpll_hw_state *dpll_hw_state); + /* SKL dpll related functions */ bool skl_ddi_dp_set_dpll_hw_state(int clock, struct intel_dpll_hw_state *dpll_hw_state); + +/* HSW dpll related functions */ +struct intel_shared_dpll *hsw_ddi_dp_get_dpll(struct intel_encoder *encoder, + int clock); + #endif /* _INTEL_DPLL_MGR_H_ */ |