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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-03-08 18:46:21 +0300
committerAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-03-09 12:55:31 +0300
commit2edd6443e3d03267bfc63071a86332a1711dc1bc (patch)
treec1c2db92cc5f7e0f9467d40ff3fdc3f199d05459 /drivers/gpu/drm/i915/intel_dpll_mgr.h
parentc2a9fcd6831aee2944f5e6d3858f56f35a2ed70a (diff)
downloadlinux-2edd6443e3d03267bfc63071a86332a1711dc1bc.tar.xz
drm/i915: Use a table to initilize shared dplls
Use a table to store the per-platform shared dpll information in one place. This way, there is no need for platform specific init funtions. Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1457451987-17466-8-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dpll_mgr.h')
-rw-r--r--drivers/gpu/drm/i915/intel_dpll_mgr.h22
1 files changed, 14 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index a2ecf80239f3..8be2478af78f 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -28,6 +28,7 @@
struct drm_i915_private;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_shared_dpll;
enum intel_dpll_id {
DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
@@ -78,14 +79,7 @@ struct intel_shared_dpll_config {
struct intel_dpll_hw_state hw_state;
};
-struct intel_shared_dpll {
- struct intel_shared_dpll_config config;
-
- int active; /* count of number of active CRTCs (i.e. DPMS on) */
- bool on; /* is the PLL actually active? Disabled during modeset */
- const char *name;
- /* should match the index in the dev_priv->shared_dplls array */
- enum intel_dpll_id id;
+struct intel_shared_dpll_funcs {
/* The mode_set hook is optional and should be used together with the
* intel_prepare_shared_dpll function. */
void (*mode_set)(struct drm_i915_private *dev_priv,
@@ -99,6 +93,18 @@ struct intel_shared_dpll {
struct intel_dpll_hw_state *hw_state);
};
+struct intel_shared_dpll {
+ struct intel_shared_dpll_config config;
+
+ int active; /* count of number of active CRTCs (i.e. DPMS on) */
+ bool on; /* is the PLL actually active? Disabled during modeset */
+ const char *name;
+ /* should match the index in the dev_priv->shared_dplls array */
+ enum intel_dpll_id id;
+
+ struct intel_shared_dpll_funcs funcs;
+};
+
#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2