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| author | Sonika Jindal <sonika.jindal@intel.com> | 2015-03-05 07:33:58 +0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-18 00:29:56 +0300 |
| commit | fc0f8e25318f4850fc02e2d1a19a41daf69820c4 (patch) | |
| tree | 71dc270510742536fc9ff0d649afc858fd78713e /drivers/gpu/drm/i915/intel_dp.c | |
| parent | dbef0f15b5c83231dacb214dbf9a6dba063ca21c (diff) | |
| download | linux-fc0f8e25318f4850fc02e2d1a19a41daf69820c4.tar.xz | |
drm/i915/skl: Read sink supported rates from edp panel
v2: Using DP_SUPPORTED_LINK_RATES macro for supported_rates array (Satheesh).
v3: Reading dpcd's supported link rates tables based upon edp version in the
same patch.
v4: Move version check under is_edp (Satheesh)
v5: Using le16 for rates, some naming, and removing nested if block (Ville)
v6: Correctly using DP_MAX_SUPPORTED_RATES and removing DP_SUPPORTED_LINK_RATES
(Ville)
v7: Incorrectly removed DP_SUPPORTED_LINK_RATES in v6, re-adding it
v8: Checking return value of intel_dp_dpcd_read_wake() (Ville)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp.c')
| -rw-r--r-- | drivers/gpu/drm/i915/intel_dp.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 0a57763e73fa..18d4a7cad652 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1117,6 +1117,33 @@ hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config, int link_bw) } } +static int +intel_read_sink_rates(struct intel_dp *intel_dp, uint32_t *sink_rates) +{ + struct drm_device *dev = intel_dp_to_dev(intel_dp); + int i = 0; + uint16_t val; + + if (INTEL_INFO(dev)->gen >= 9 && intel_dp->supported_rates[0]) { + /* + * Receiver supports only main-link rate selection by + * link rate table method, so read link rates from + * supported_link_rates + */ + for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i) { + val = le16_to_cpu(intel_dp->supported_rates[i]); + if (val == 0) + break; + + sink_rates[i] = val * 200; + } + + if (i <= 0) + DRM_ERROR("No rates in SUPPORTED_LINK_RATES"); + } + return i; +} + static void intel_dp_set_clock(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, int link_bw) @@ -3578,6 +3605,7 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = dev->dev_private; + uint8_t rev; if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd, sizeof(intel_dp->dpcd)) < 0) @@ -3609,6 +3637,16 @@ intel_dp_get_dpcd(struct intel_dp *intel_dp) } else intel_dp->use_tps3 = false; + /* Intermediate frequency support */ + if (is_edp(intel_dp) && + (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) && + (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) && + (rev >= 0x03)) { /* eDp v1.4 or higher */ + intel_dp_dpcd_read_wake(&intel_dp->aux, + DP_SUPPORTED_LINK_RATES, + intel_dp->supported_rates, + sizeof(intel_dp->supported_rates)); + } if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) return true; /* native DP sink */ |