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| author | Clint Taylor <clinton.a.taylor@intel.com> | 2017-06-10 01:26:09 +0300 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2017-06-12 19:44:17 +0300 |
| commit | 0091abc3a621f4acf41e35ea00a4ab4f064c2fb7 (patch) | |
| tree | 3c3b9d396c70516c2cc12418033ee6069f53dd91 /drivers/gpu/drm/i915/intel_csr.c | |
| parent | cf54ca8bc5674049889d208131cb1b0e15161a2c (diff) | |
| download | linux-0091abc3a621f4acf41e35ea00a4ab4f064c2fb7.tar.xz | |
drm/i915/cnl: Enable loadgen_select bit for vswing sequence
vswing programming sequence step 2 requires the Loadgen_select bit to
be set in PORT_TX_DW4 lane reigsters per table defined by Bit rate and
lane width. Implemented the change that was marked as FIXME in the
driver.
v2: (Rodrigo) checkpatch fixes.
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1497047175-27250-12-git-send-email-rodrigo.vivi@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/intel_csr.c')
0 files changed, 0 insertions, 0 deletions