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| author | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2014-06-06 01:28:17 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-06-13 17:17:41 +0400 |
| commit | a8aab8bd5efe1377ea2b0d2b51b26989eea6906d (patch) | |
| tree | cc6399516a81730934f61f9b0f3e4ef31073ccde /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 75a91c975b7d127182ac5742277d33a310560be8 (diff) | |
| download | linux-a8aab8bd5efe1377ea2b0d2b51b26989eea6906d.tar.xz | |
drm/i915: Fix VLV CRC reading.
Adding missing Display mmio reg offset.
Credits-to: Laws, Philip <philip.laws@intel.com>
Cc: He, Shuang <shuang.he@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 286f05c63047..05e2541077ea 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2627,7 +2627,7 @@ enum punit_power_well { #define PORT_DFT_I9XX 0x61150 #define DC_BALANCE_RESET (1 << 25) -#define PORT_DFT2_G4X 0x61154 +#define PORT_DFT2_G4X (dev_priv->info.display_mmio_offset + 0x61154) #define DC_BALANCE_RESET_VLV (1 << 31) #define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0) #define PIPE_B_SCRAMBLE_RESET (1 << 1) |