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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-03-12 22:57:43 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2019-03-14 00:20:21 +0300 |
| commit | 8a9a5608a31b23a8da4be67285176dd4cacfa574 (patch) | |
| tree | 7a982780d00ae8759c2dfb9d594df5eee5e3d428 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 1e0c05c09037c593f0c06054a28c1021e13e8dfa (diff) | |
| download | linux-8a9a5608a31b23a8da4be67285176dd4cacfa574.tar.xz | |
drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1
When any other value than EDP_PSR_TP4_TIME_0US is set, TPS1 and TPS4
will be used to do the link training when exiting PSR1.
Happily the eDP panels tested so far was able to sync with source
even without HBR3/TPS4 support but let use the right training
pattern.
TPS4 support was added to PSR1 registers because HBR3/PSR
specification was not closed when ICL was freezed so if HBR3 was
supported by PSR, ICL would already be ready but it was not added to
specification so lets always disable TPS4.
v3: Missed ";" SPANK SPANK SPANK!!!
BSpec: 17524
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190312195743.8829-3-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 87123861e41e..9b69cec21f7b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4205,6 +4205,7 @@ enum { #define EDP_PSR_TP2_TP3_TIME_100us (1 << 8) #define EDP_PSR_TP2_TP3_TIME_2500us (2 << 8) #define EDP_PSR_TP2_TP3_TIME_0us (3 << 8) +#define EDP_PSR_TP4_TIME_0US (3 << 6) /* ICL+ */ #define EDP_PSR_TP1_TIME_500us (0 << 4) #define EDP_PSR_TP1_TIME_100us (1 << 4) #define EDP_PSR_TP1_TIME_2500us (2 << 4) |