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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-10-18 13:49:51 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-11-12 02:51:03 +0400 |
| commit | 4358a3748c39de3e66b6dc260af7a5ef785e120b (patch) | |
| tree | fe85b8c630dc0f203216ca665f46690dd2c21c2e /drivers/gpu/drm/i915/i915_reg.h | |
| parent | a8b1397d717e36abd9e45f8fee61d800f7d236ec (diff) | |
| download | linux-4358a3748c39de3e66b6dc260af7a5ef785e120b.tar.xz | |
drm/i915: implement WaDisableRenderCachePipelinedFlush
Comment says for eaglelake/cantiga, but it's listed in the ilk table,
too. So apply it to both.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 876af8e28295..0514823e561b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -670,6 +670,7 @@ #define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */ #define CACHE_MODE_0 0x02120 /* 915+ only */ +#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8) #define CM0_IZ_OPT_DISABLE (1<<6) #define CM0_ZR_OPT_DISABLE (1<<5) #define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) |