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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2013-11-03 08:07:46 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-11-08 21:09:59 +0400 |
| commit | 416f4727abf9e5ecc88fea4b55ea294d310534ac (patch) | |
| tree | 1add8447458d00e7567b7c005b430655e3841845 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 77d8d00944dd5a0a2f4f67809819df927ee23030 (diff) | |
| download | linux-416f4727abf9e5ecc88fea4b55ea294d310534ac.tar.xz | |
drm/i915/bdw: Add Broadwell display FIFO limits
Broadwell has bigger display FIFOs than Haswell. Otherwise the
two are very similar.
v2: Fix FBC WM_LP shift for BDW
v3: Rebase on top of the big Haswell wm rework.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2)
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ad903b927fb8..b2abdd78fdef 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3379,6 +3379,7 @@ #define WM1_LP_LATENCY_MASK (0x7f<<24) #define WM1_LP_FBC_MASK (0xf<<20) #define WM1_LP_FBC_SHIFT 20 +#define WM1_LP_FBC_SHIFT_BDW 19 #define WM1_LP_SR_MASK (0x7ff<<8) #define WM1_LP_SR_SHIFT 8 #define WM1_LP_CURSOR_MASK (0xff) |