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author | Eric Anholt <eric@anholt.net> | 2012-01-03 21:23:29 +0400 |
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committer | Keith Packard <keithp@keithp.com> | 2012-01-03 21:31:18 +0400 |
commit | ae662d31264979e52581bd2573bf0b82812f52ab (patch) | |
tree | 678d7f4483b6fe9a78e1ece0cb8bdefe1582dcf0 /drivers/gpu/drm/i915/i915_irq.c | |
parent | e959b5db4aacc27bcf92889e658445326ebc4bfb (diff) | |
download | linux-ae662d31264979e52581bd2573bf0b82812f52ab.tar.xz |
drm/i915: Add support for resetting the SO write pointers on gen7.
These registers are automatically incremented by the hardware during
transform feedback to track where the next streamed vertex output
should go. Unlike the previous generation, which had a packet for
setting the corresponding registers to a defined value, gen7 only has
MI_LOAD_REGISTER_IMM to do so. That's a secure packet (since it loads
an arbitrary register), so we need to do it from the kernel, and it
needs to be settable atomically with the batchbuffer execution so that
two clients doing transform feedback don't stomp on each others'
state.
Instead of building a more complicated interface involcing setting the
registers to a specific value, just set them to 0 when asked and
userland can tweak its pointers accordingly.
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
0 files changed, 0 insertions, 0 deletions