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| author | Chris Wilson <chris@chris-wilson.co.uk> | 2014-03-27 12:24:19 +0400 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2014-03-31 12:46:34 +0400 |
| commit | 037bde19a43e299d30f0490bba9be32ab355975c (patch) | |
| tree | 41733f741e38af8af92705e11f758be785ffc944 /drivers/gpu/drm/i915/i915_irq.c | |
| parent | 1caea6e945e0867d391369097937620c945dcec1 (diff) | |
| download | linux-037bde19a43e299d30f0490bba9be32ab355975c.tar.xz | |
Revert "drm/i915: Disable/Enable PM Intrrupts based on the current freq."
This reverts commit 2754436913b94626a5414d82f0996489628c513d.
Conflicts:
drivers/gpu/drm/i915/i915_irq.c
The partial application of interrupt masking without regard to other
pathways for adjusting the RPS frequency results in completely disabling
the PM interrupts. This leads to excessive power consumption as the GPU
is kept at max clocks (until the failsafe mechanism fires of explicitly
downclocking the GPU when all requests are idle). Or equally as bad for
the UX, the GPU is kept at minimum clocks and prevented from upclocking
in response to a requirement for more power.
Testcase: pm_rps/blocking
Cc: Deepak S <deepak.s@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by:Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_irq.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_irq.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index f5a74b70f5e5..72e26e2be301 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1084,43 +1084,6 @@ static void notify_ring(struct drm_device *dev, i915_queue_hangcheck(dev); } -void gen6_set_pm_mask(struct drm_i915_private *dev_priv, - u32 pm_iir, int new_delay) -{ - if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) { - if (new_delay >= dev_priv->rps.max_freq_softlimit) { - /* Mask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = true; - } - if (dev_priv->rps.rp_down_masked) { - /* UnMask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = false; - } - } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { - if (new_delay <= dev_priv->rps.min_freq_softlimit) { - /* Mask DOWN THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) | - GEN6_PM_RP_DOWN_THRESHOLD); - dev_priv->rps.rp_down_masked = true; - } - - if (dev_priv->rps.rp_up_masked) { - /* UnMask UP THRESHOLD Interrupts */ - I915_WRITE(GEN6_PMINTRMSK, - I915_READ(GEN6_PMINTRMSK) & - ~GEN6_PM_RP_UP_THRESHOLD); - dev_priv->rps.rp_up_masked = false; - } - } -} - static void gen6_pm_rps_work(struct work_struct *work) { drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t, @@ -1180,7 +1143,6 @@ static void gen6_pm_rps_work(struct work_struct *work) dev_priv->rps.min_freq_softlimit, dev_priv->rps.max_freq_softlimit); - gen6_set_pm_mask(dev_priv, pm_iir, new_delay); dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_freq; if (IS_VALLEYVIEW(dev_priv->dev)) |