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authorVille Syrjälä <ville.syrjala@linux.intel.com>2017-03-09 18:44:34 +0300
committerVille Syrjälä <ville.syrjala@linux.intel.com>2017-03-13 22:15:10 +0300
commit44e921d4a19846e39fa818afa9d2d22c3117210a (patch)
tree54dd567690fcac683a0d8bdd8ee8aae080f57a89 /drivers/gpu/drm/i915/i915_drv.h
parentdd584fc0711a28fb338bf66a623178e468c82272 (diff)
downloadlinux-44e921d4a19846e39fa818afa9d2d22c3117210a.tar.xz
drm/i915: Optimize VLV/CHV display FIFO updates
Use I915_{READ,WRITE}_FW() for updating the DSPARB registers on VLV/CHV. This is less expesive as we can grab the uncore.lock across the entire sequence of reads and writes instead of each register access grabbing it. This also allows us to eliminate the dsparb lock entirely as the uncore.lock now effectively protects the contents of the DSPARB registers. v2: Add a note that interrupts are already disabled (Chris) Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/20170309154434.29303-6-ville.syrjala@linux.intel.com Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h3
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d11c96405a53..48ff64812289 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2375,9 +2375,6 @@ struct drm_i915_private {
} sagv_status;
struct {
- /* protects DSPARB registers on pre-g4x/vlv/chv */
- spinlock_t dsparb_lock;
-
/*
* Raw watermark latency values:
* in 0.1us units for WM0,