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authorAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-04-27 15:44:22 +0300
committerAnder Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com>2016-04-29 09:57:36 +0300
commit53d9872511c4911616ae39f59d97afb62510d81e (patch)
tree100a26b4221ce5c21a238f404b24f5b75ed969a1 /drivers/gpu/drm/i915/i915_drv.h
parent204970b5cf8a3d3367b346df0ec6f56279ad8fca (diff)
downloadlinux-53d9872511c4911616ae39f59d97afb62510d81e.tar.xz
drm/i915: Unduplicate VLV signal level code
The logic for setting signal levels is used for both HDMI and DP with small variations. But it is similar enough to put behind a function called from the encoders. v2: Remove unrelated MST changes due to rebase fumble. (Jim Bride) Fix typo in the commit message. (Jim Bride) v3: Really fix the typo. (Jim) Cc: Jim Bride <jim.bride@linux.intel.com> Signed-off-by: Ander Conselvan de Oliveira <ander.conselvan.de.oliveira@intel.com> Reviewed-by: Jim Bride <jim.bride@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1461761065-21195-8-git-send-email-ander.conselvan.de.oliveira@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/i915_drv.h')
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 2f4fe7ef1a26..7bdbea5e1255 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3600,6 +3600,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder);
void chv_phy_release_cl2_override(struct intel_encoder *encoder);
void chv_phy_post_pll_disable(struct intel_encoder *encoder);
+void vlv_set_phy_signal_level(struct intel_encoder *encoder,
+ u32 demph_reg_value, u32 preemph_reg_value,
+ u32 uniqtranscale_reg_value, u32 tx3_demph);
+
int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);