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author | Gwan-gyeong Mun <gwan-gyeong.mun@intel.com> | 2020-05-14 09:07:32 +0300 |
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committer | Jani Nikula <jani.nikula@intel.com> | 2020-05-14 13:54:17 +0300 |
commit | 7a00e68b431716d9258cbf4dc72c307ac39e8733 (patch) | |
tree | 88422d41ed13952b58457a9144fc17b82a46f8a7 /drivers/gpu/drm/i915/gvt | |
parent | cafac5a983619944afa639c53f0d5d885616a3d2 (diff) | |
download | linux-7a00e68b431716d9258cbf4dc72c307ac39e8733.tar.xz |
drm/i915/psr: Use new DP VSC SDP compute routine on PSR
In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.
In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.
There are no changes to PSR mechanism.
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
v8: Rebased
v10: When a PSR is enabled, it needs to add DP_SDP_VSC to
infoframes.enable.
It is needed for comparing between HW and pipe_state of VSC_SDP.
v11: If PSR is disabled by flag, it don't enable psr on pipe compute.
v12: Fix an inconsistent indenting
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-15-gwan-gyeong.mun@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt')
0 files changed, 0 insertions, 0 deletions