diff options
| author | Min He <min.he@intel.com> | 2017-02-17 10:02:36 +0300 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2017-02-17 11:03:38 +0300 |
| commit | fd64be636708d808852c4c8c1efce0a0a51c24c5 (patch) | |
| tree | 1a5fa8ae968cf2edc33134812a30f1693a4adcba /drivers/gpu/drm/i915/gvt/vgpu.c | |
| parent | f655e67ac8d797425abb0404d0878758f3f71c1a (diff) | |
| download | linux-fd64be636708d808852c4c8c1efce0a0a51c24c5.tar.xz | |
drm/i915/gvt: introduced failsafe mode into vgpu
New failsafe mode is introduced, when we detect guest not supporting
GVT-g.
In failsafe mode, we will ignore all the MMIO and cfg space read/write
from guest.
This patch can fix the issue that when guest kernel or graphics driver
version is too low, there will be a lot of kernel traces in host.
V5: rebased onto latest gvt-staging
V4: changed coding style by Zhenyu and Ping's advice
V3: modified coding style and error messages according to Zhenyu's comment
V2: 1) implemented MMIO/GTT/WP pages read/write logic; 2) used a unified
function to enter failsafe mode
Signed-off-by: Min He <min.he@intel.com>
Signed-off-by: Pei Zhang <pei.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/vgpu.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/vgpu.c | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/vgpu.c b/drivers/gpu/drm/i915/gvt/vgpu.c index 95a97aa0051e..dcfcce1dc00e 100644 --- a/drivers/gpu/drm/i915/gvt/vgpu.c +++ b/drivers/gpu/drm/i915/gvt/vgpu.c @@ -387,8 +387,12 @@ void intel_gvt_reset_vgpu_locked(struct intel_vgpu *vgpu, bool dmlr, populate_pvinfo_page(vgpu); intel_vgpu_reset_display(vgpu); - if (dmlr) + if (dmlr) { intel_vgpu_reset_cfg_space(vgpu); + /* only reset the failsafe mode when dmlr reset */ + vgpu->failsafe = false; + vgpu->pv_notified = false; + } } vgpu->resetting = false; |