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authorZhi Wang <zhi.a.wang@intel.com>2017-09-10 16:33:20 +0300
committerZhenyu Wang <zhenyuw@linux.intel.com>2017-11-16 06:46:49 +0300
commit91d5d85442b2a65e5f4e1726565c1c1a8ba9976f (patch)
tree79479bc6ae6da2b8fbbb27964f4e188436b6c5c5 /drivers/gpu/drm/i915/gvt/render.c
parent1406a14b0ed977fc18f43398b391e4bb5d744174 (diff)
downloadlinux-91d5d85442b2a65e5f4e1726565c1c1a8ba9976f.tar.xz
drm/i915/gvt: Move tlb_handle_pending into intel_vgpu_submission
Move tlb_handle_pending into intel_vgpu_submssion since it belongs to a part of vGPU submission stuffs Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/render.c')
-rw-r--r--drivers/gpu/drm/i915/gvt/render.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/render.c b/drivers/gpu/drm/i915/gvt/render.c
index db4d091be60b..e16c3551b4a3 100644
--- a/drivers/gpu/drm/i915/gvt/render.c
+++ b/drivers/gpu/drm/i915/gvt/render.c
@@ -147,6 +147,7 @@ static u32 gen9_render_mocs_L3[32];
static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+ struct intel_vgpu_submission *s = &vgpu->submission;
enum forcewake_domains fw;
i915_reg_t reg;
u32 regs[] = {
@@ -160,7 +161,7 @@ static void handle_tlb_pending_event(struct intel_vgpu *vgpu, int ring_id)
if (WARN_ON(ring_id >= ARRAY_SIZE(regs)))
return;
- if (!test_and_clear_bit(ring_id, (void *)vgpu->tlb_handle_pending))
+ if (!test_and_clear_bit(ring_id, (void *)s->tlb_handle_pending))
return;
reg = _MMIO(regs[ring_id]);