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author | Zhi Wang <zhi.a.wang@intel.com> | 2015-09-17 04:22:08 +0300 |
---|---|---|
committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2016-10-14 13:12:22 +0300 |
commit | c8fe6a6811a7186656379d0c27e85325a966077a (patch) | |
tree | ee8294cf5ff5d49dcc95d868b1b6d75f7d08c323 /drivers/gpu/drm/i915/gvt/gvt.c | |
parent | 3f728236c5166052f88474412059cc63540cd27a (diff) | |
download | linux-c8fe6a6811a7186656379d0c27e85325a966077a.tar.xz |
drm/i915/gvt: vGPU interrupt virtualization.
This patch introduces vGPU interrupt emulation framework.
The vGPU intrerrupt emulation framework is an event-based interrupt
emulation framework. It's responsible for emulating GEN hardware interrupts
during emulating other HW behaviour.
It consists several components:
- Descriptions of interrupt register bit
- Upper level <-> lower level interrupt mapping
- GEN HW IER/IMR/IIR register emulation routines
- Event-based interrupt propagation interface
When a GVT-g component wants to inject an interrupt to a VM during a
emulation, first it should specify the event needs to be emulated and the
framework will deal with the rest of emulation:
- Generating related virtual IIR bit according to virtual IER and IMRs,
- Generate related virtual upper level virtual IIR bit accodring to the
per-platform interrupt mapping
- Injecting a MSI to VM
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/gvt.c')
-rw-r--r-- | drivers/gpu/drm/i915/gvt/gvt.c | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gvt.c b/drivers/gpu/drm/i915/gvt/gvt.c index 2c03dad28718..29efe454b1cd 100644 --- a/drivers/gpu/drm/i915/gvt/gvt.c +++ b/drivers/gpu/drm/i915/gvt/gvt.c @@ -97,9 +97,10 @@ static void init_device_info(struct intel_gvt *gvt) if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv)) { info->max_support_vgpus = 8; - info->mmio_size = 2 * 1024 * 1024; info->cfg_space_size = 256; + info->mmio_size = 2 * 1024 * 1024; info->mmio_bar = 0; + info->msi_cap_offset = IS_SKYLAKE(gvt->dev_priv) ? 0xac : 0x90; } } @@ -118,6 +119,7 @@ void intel_gvt_clean_device(struct drm_i915_private *dev_priv) if (WARN_ON(!gvt->initialized)) return; + intel_gvt_clean_irq(gvt); intel_gvt_clean_mmio_info(gvt); intel_gvt_free_firmware(gvt); @@ -165,10 +167,16 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv) if (ret) goto out_clean_mmio_info; + ret = intel_gvt_init_irq(gvt); + if (ret) + goto out_free_firmware; + gvt_dbg_core("gvt device creation is done\n"); gvt->initialized = true; return 0; +out_free_firmware: + intel_gvt_free_firmware(gvt); out_clean_mmio_info: intel_gvt_clean_mmio_info(gvt); return ret; |