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| author | Matt Roper <matthew.d.roper@intel.com> | 2022-05-06 00:38:07 +0300 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2022-05-11 01:31:05 +0300 |
| commit | 93d9e0453e2bb599e0bcced1b914f9b4010180a1 (patch) | |
| tree | 34dbe20021bbdebf892eafdf4d84cdf3d7034c49 /drivers/gpu/drm/i915/gvt/cmd_parser.c | |
| parent | 6cd96877c7da6bc3a28ef0bcb3bc7470f4dd9aa6 (diff) | |
| download | linux-93d9e0453e2bb599e0bcced1b914f9b4010180a1.tar.xz | |
drm/i915/gvt: Use intel_engine_mask_t for ring mask
When i915 adds additional PVC blitter instances (in an upcoming patch),
the definition of VECS0 will change from bit(10) to bit(18), causing
GVT's R_ALL mask to overflow the u16 storage that's currently used.
Let's replace the u16 with an intel_engine_mask_t to ensure we avoid
this.
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505213812.3979301-8-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gvt/cmd_parser.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gvt/cmd_parser.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index 2459213b6c87..efad8552d6e6 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -428,7 +428,7 @@ struct cmd_info { #define R_VECS BIT(VECS0) #define R_ALL (R_RCS | R_VCS | R_BCS | R_VECS) /* rings that support this cmd: BLT/RCS/VCS/VECS */ - u16 rings; + intel_engine_mask_t rings; /* devices that support this cmd: SNB/IVB/HSW/... */ u16 devices; |