diff options
| author | José Roberto de Souza <jose.souza@intel.com> | 2020-03-03 02:14:20 +0300 |
|---|---|---|
| committer | José Roberto de Souza <jose.souza@intel.com> | 2020-03-04 00:32:52 +0300 |
| commit | 3551ff92874405674b58ac0f5742069a5ddfc462 (patch) | |
| tree | ffea3b8342e8e310f6c8afd32b8880fe1c3602a8 /drivers/gpu/drm/i915/gt | |
| parent | 9b234d2643692601149b373e5d7e831eace95dfa (diff) | |
| download | linux-3551ff92874405674b58ac0f5742069a5ddfc462.tar.xz | |
drm/i915/gen11: Moving WAs to rcs_engine_wa_init()
This are register of render engine, so after a render reset those
would return to the default value and init_clock_gating() is not
called for single engine reset.
So here moving it rcs_engine_wa_init() that will guarantee that this
WAs will not be lost.
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302231421.224322-1-jose.souza@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_workarounds.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 3e375a3b7714..90e1c48dd6be 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -1454,6 +1454,21 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) GEN11_SCRATCH2, GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE, 0); + + /* WaEnable32PlaneMode:icl */ + wa_masked_en(wal, GEN9_CSFE_CHICKEN1_RCS, + GEN11_ENABLE_32_PLANE_MODE); + + /* + * Wa_1408615072:icl,ehl (vsunit) + * Wa_1407596294:icl,ehl (hsunit) + */ + wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE, + VSUNIT_CLKGATE_DIS | HSUNIT_CLKGATE_DIS); + + /* Wa_1407352427:icl,ehl */ + wa_masked_en(wal, UNSLICE_UNIT_LEVEL_CLKGATE2, + PSDUNIT_CLKGATE_DIS); } if (IS_GEN_RANGE(i915, 9, 11)) { |