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author | Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-29 12:16:32 +0300 |
---|---|---|
committer | Chris Wilson <chris@chris-wilson.co.uk> | 2019-10-29 19:23:55 +0300 |
commit | b79029b2e859d8cef534643a1254a833459038f1 (patch) | |
tree | a371089353ac9275d67f8b8b4a825352090b5e15 /drivers/gpu/drm/i915/gt/intel_engine.h | |
parent | 4ec37538a6670a4f0291e4a1de9394908e0f0d08 (diff) | |
download | linux-b79029b2e859d8cef534643a1254a833459038f1.tar.xz |
drm/i915/gt: Make timeslice duration configurable
Execlists uses a scheduling quantum (a timeslice) to alternate execution
between ready-to-run contexts of equal priority. This ensures that all
users (though only if they of equal importance) have the opportunity to
run and prevents livelocks where contexts may have implicit ordering due
to userspace semaphores. However, not all workloads necessarily benefit
from timeslicing and in the extreme some sysadmin may want to disable or
reduce the timeslicing granularity.
The timeslicing mechanism can be compiled out^W^W disabled (but should
DCE!) with
./scripts/config --set-val DRM_I915_TIMESLICE_DURATION 0
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191029091632.26281-1-chris@chris-wilson.co.uk
Diffstat (limited to 'drivers/gpu/drm/i915/gt/intel_engine.h')
-rw-r--r-- | drivers/gpu/drm/i915/gt/intel_engine.h | 13 |
1 files changed, 11 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h index c6895938b626..bc3b72bfa9e3 100644 --- a/drivers/gpu/drm/i915/gt/intel_engine.h +++ b/drivers/gpu/drm/i915/gt/intel_engine.h @@ -329,10 +329,19 @@ void intel_engine_init_active(struct intel_engine_cs *engine, static inline bool intel_engine_has_preempt_reset(const struct intel_engine_cs *engine) { - if (!CONFIG_DRM_I915_PREEMPT_TIMEOUT) - return 0; + if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT)) + return false; return intel_engine_has_preemption(engine); } +static inline bool +intel_engine_has_timeslices(const struct intel_engine_cs *engine) +{ + if (!IS_ACTIVE(CONFIG_DRM_I915_TIMESLICE_DURATION)) + return false; + + return intel_engine_has_semaphores(engine); +} + #endif /* _INTEL_RINGBUFFER_H_ */ |