diff options
| author | Imre Deak <imre.deak@intel.com> | 2023-06-06 20:28:22 +0300 |
|---|---|---|
| committer | Tvrtko Ursulin <tvrtko.ursulin@intel.com> | 2023-06-26 11:17:39 +0300 |
| commit | a6b4229d858ed4db6ad68854bb8a2f7d5ac9f138 (patch) | |
| tree | 6418c26bf356090872997fdc2aa6b25fb7c07880 /drivers/gpu/drm/i915/display | |
| parent | 274d4b96b12f78cef4f72a97a4967032233f6cae (diff) | |
| download | linux-a6b4229d858ed4db6ad68854bb8a2f7d5ac9f138.tar.xz | |
drm/i915/adlp+: Allow DC states along with PW2 only for PWB functionality
A recent bspec update added a restriction on when DC states can be enabled:
[Before enabling DC states:]
"""
PG2 can be kept enabled only because PGB requires PG2.
Do not use PG2 functions, such as type-C DDIs.
DMC will dynamically control PG1, PGA, PG2, PGB.
"""
Accordingly prevent DC states if PW2 (aka PG2) is enabled for any other
functionality.
Bpsec: 49193
Fixes: 88c487938414 ("drm/i915: Use separate "DC off" power well for ADL-P and DG2")
Reported-by: Kai Vehmanen <kai.vehmanen@intel.com>
Tested-by: Ambica Pramod <ambica.pramod@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230606172822.1891897-1-imre.deak@intel.com
(cherry picked from commit f4e498eb1247d25231198856b57bbae00f403c85)
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_power_map.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c index 1118ee9d224c..5ad04cd42c15 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c @@ -1252,10 +1252,18 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, POWER_DOMAIN_INIT); #define XELPD_DC_OFF_PORT_POWER_DOMAINS \ + POWER_DOMAIN_PORT_DDI_LANES_C, \ + POWER_DOMAIN_PORT_DDI_LANES_D, \ + POWER_DOMAIN_PORT_DDI_LANES_E, \ POWER_DOMAIN_PORT_DDI_LANES_TC1, \ POWER_DOMAIN_PORT_DDI_LANES_TC2, \ POWER_DOMAIN_PORT_DDI_LANES_TC3, \ POWER_DOMAIN_PORT_DDI_LANES_TC4, \ + POWER_DOMAIN_VGA, \ + POWER_DOMAIN_AUDIO_PLAYBACK, \ + POWER_DOMAIN_AUX_IO_C, \ + POWER_DOMAIN_AUX_IO_D, \ + POWER_DOMAIN_AUX_IO_E, \ POWER_DOMAIN_AUX_C, \ POWER_DOMAIN_AUX_D, \ POWER_DOMAIN_AUX_E, \ @@ -1272,14 +1280,6 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a, XELPD_PW_B_POWER_DOMAINS, \ XELPD_PW_C_POWER_DOMAINS, \ XELPD_PW_D_POWER_DOMAINS, \ - POWER_DOMAIN_PORT_DDI_LANES_C, \ - POWER_DOMAIN_PORT_DDI_LANES_D, \ - POWER_DOMAIN_PORT_DDI_LANES_E, \ - POWER_DOMAIN_VGA, \ - POWER_DOMAIN_AUDIO_PLAYBACK, \ - POWER_DOMAIN_AUX_IO_C, \ - POWER_DOMAIN_AUX_IO_D, \ - POWER_DOMAIN_AUX_IO_E, \ XELPD_DC_OFF_PORT_POWER_DOMAINS I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2, |