diff options
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-02-06 00:46:20 +0300 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2021-02-16 15:24:49 +0300 |
| commit | ad9529824cafbee214dbf580228e4c390dc61a58 (patch) | |
| tree | 67d5947df062ecf09a9cfc8168eda508e75d9c88 /drivers/gpu/drm/i915/display/intel_fdi.c | |
| parent | f3243b75dbc7f305806adaaca379338e25dba755 (diff) | |
| download | linux-ad9529824cafbee214dbf580228e4c390dc61a58.tar.xz | |
drm/i915: Use intel_ddi_clk_select() for FDI
We want to put all DDI clock routing code into one place.
Unify the FDI enable sequence to use the standard function
instead of hand rolling its own. The disable sequence already
uses the normal thing.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210205214634.19341-2-ville.syrjala@linux.intel.com
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_fdi.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_fdi.c | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c index 77df675e607e..dbd6be3342c0 100644 --- a/drivers/gpu/drm/i915/display/intel_fdi.c +++ b/drivers/gpu/drm/i915/display/intel_fdi.c @@ -565,7 +565,7 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - u32 temp, i, rx_ctl_val, ddi_pll_sel; + u32 temp, i, rx_ctl_val; int n_entries; intel_ddi_get_buf_trans_fdi(dev_priv, &n_entries); @@ -595,9 +595,8 @@ void hsw_fdi_link_train(struct intel_encoder *encoder, intel_de_write(dev_priv, FDI_RX_CTL(PIPE_A), rx_ctl_val); /* Configure Port Clock Select */ - ddi_pll_sel = hsw_pll_to_ddi_pll_sel(crtc_state->shared_dpll); - intel_de_write(dev_priv, PORT_CLK_SEL(PORT_E), ddi_pll_sel); - drm_WARN_ON(&dev_priv->drm, ddi_pll_sel != PORT_CLK_SEL_SPLL); + drm_WARN_ON(&dev_priv->drm, crtc_state->shared_dpll->info->id != DPLL_ID_SPLL); + intel_ddi_clk_select(encoder, crtc_state); /* Start the training iterating through available voltages and emphasis, * testing each value twice. */ |