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| author | Jouni Högander <jouni.hogander@intel.com> | 2025-04-14 13:05:06 +0300 |
|---|---|---|
| committer | Jouni Högander <jouni.hogander@intel.com> | 2025-04-23 12:16:31 +0300 |
| commit | 39e4d3c2f89ab88450c5aea0477d5c32a7d5502f (patch) | |
| tree | 66b9e15f240e14688cf433c1ab2fc88c1b66d335 /drivers/gpu/drm/i915/display/intel_display_irq.c | |
| parent | 2978eb1841cd635f17e568ad74ffa32f68fcd54d (diff) | |
| download | linux-39e4d3c2f89ab88450c5aea0477d5c32a7d5502f.tar.xz | |
drm/i915/psr: Apply underrun on PSR idle workaround
This patch is applying workaround for underrun on idle PSR HW issue
(Wa_16025596647) when PSR is getting enabled. It uses vblank enable/disable
status, DC5/6 enabled disabled and enabled pipes count information made
available.
This patch is also adding calls to dc5/dc6, vblank enable/disable and pipe
enable/disable notification functions as needed.
intel_psr_needs_block_dc_vblank is modified to get vblank enable/disable
notification on PSR capable system.
v2: use intel_dmc interface instead of directly writing dmc register
Bspec: 74151
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://lore.kernel.org/r/20250414100508.1208774-12-jouni.hogander@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_display_irq.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_display_irq.c | 9 |
1 files changed, 1 insertions, 8 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c index 2e34af6e40f0..ab1d96924494 100644 --- a/drivers/gpu/drm/i915/display/intel_display_irq.c +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c @@ -1704,14 +1704,7 @@ static void intel_display_vblank_dc_work(struct work_struct *work) container_of(work, typeof(*display), irq.vblank_dc_work); int vblank_wa_num_pipes = READ_ONCE(display->irq.vblank_wa_num_pipes); - /* - * NOTE: intel_display_power_set_target_dc_state is used only by PSR - * code for DC3CO handling. DC3CO target state is currently disabled in - * PSR code. If DC3CO is taken into use we need take that into account - * here as well. - */ - intel_display_power_set_target_dc_state(display, vblank_wa_num_pipes ? DC_STATE_DISABLE : - DC_STATE_EN_UPTO_DC6); + intel_psr_notify_vblank_enable_disable(display, vblank_wa_num_pipes); } int bdw_enable_vblank(struct drm_crtc *_crtc) |